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Performance Effect of Multi-core on Scientific Applications.

DE2008923361

Publication Date	2008
Personal Author	Carter, J.; He, Y.; Shalf, J.; Shan, H.; Strohmaier, E.
Page Count	10
Abstract	The historical trend of increasing single CPU performance has given way to roadmap of increasing core count. The challenge of effectively utilizing these multi-core chips is just starting to be explored by vendors and application developers alike. In this study, we present some performance measurements of several complete scientific applications on single and dual core Cray XT3 and XT4 systems with a view to characterizing the effects of switching to multi-core chips. We consider effects within a node by using applications run at low concurrencies, and also effects on node-interconnect interaction using higher concurrency results. Finally, we construct a simple performance model based on the principle on-chip shared resource--memory bandwidth--and use this to predict the performance of the forthcoming quad-core system.
Keywords	Supercomputers Application programs(Computers) Cray computers Memory access performance Computer systems programs Chips(Electronics) Bandwidth Trends Performance evaluation
Source Agency	Technical Information Center Oak Ridge Tennessee
Corporate Authors	Lawrence Berkeley National Lab., CA.; Department of Energy, Washington, DC.
Supplemental Notes	Sponsored by Department of Energy, Washington, DC.
Document Type	Technical Report
NTIS Issue Number	200814

Performance Effect of Multi-core on Scientific Applications.

Performance Effect of Multi-core on Scientific Applications.
DE2008923361

Publication Date	2008
Personal Author	Carter, J.; He, Y.; Shalf, J.; Shan, H.; Strohmaier, E.
Page Count	10
Abstract	The historical trend of increasing single CPU performance has given way to roadmap of increasing core count. The challenge of effectively utilizing these multi-core chips is just starting to be explored by vendors and application developers alike. In this study, we present some performance measurements of several complete scientific applications on single and dual core Cray XT3 and XT4 systems with a view to characterizing the effects of switching to multi-core chips. We consider effects within a node by using applications run at low concurrencies, and also effects on node-interconnect interaction using higher concurrency results. Finally, we construct a simple performance model based on the principle on-chip shared resource--memory bandwidth--and use this to predict the performance of the forthcoming quad-core system.
Keywords	Supercomputers Application programs(Computers) Cray computers Memory access performance Computer systems programs Chips(Electronics) Bandwidth Trends Performance evaluation
Source Agency	Technical Information Center Oak Ridge Tennessee
Corporate Authors	Lawrence Berkeley National Lab., CA.; Department of Energy, Washington, DC.
Supplemental Notes	Sponsored by Department of Energy, Washington, DC.
Document Type	Technical Report
NTIS Issue Number	200814