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Architecture of the BTeV Pixel Readout Chip.

DE2003805295

Publication Date	2002
Personal Author	Christian, D. C.
Page Count	12
Abstract	The most striking feature of BTeV, a dedicated b physics experiment which is expected to begin running in 2008 in the new CZero interaction region of the Fermilab Tevatron, is that the experiment will use data from a pixel vertex detector to recon- struct tracks and vertices for every beam crossing. The lowest level trigger will be an impact parameter trigger designed to identify events containing reconstructable decays of charm and bottom particles. An R&D program to develop a pixel readout chip optimized for the Tevatron was started at Fermilab in 1997, and is now nearing completion. The architecture of the BTeV pixel readout chip is described in this paper.
Keywords	Microelectronic circuits Raiation hardening Collider detectors Readout systems Architecture BTeV Pixel readout chips Dedicated b physics Fermilab Tevatron
Source Agency	Technical Information Center Oak Ridge Tennessee
Corporate Authors	Fermi National Accelerator Lab., Batavia, IL.; Department of Energy, Washington, DC.
Supplemental Notes	Sponsored by Department of Energy, Washington, DC.
Document Type	Technical Report
NTIS Issue Number	200318

Architecture of the BTeV Pixel Readout Chip.

Architecture of the BTeV Pixel Readout Chip.
DE2003805295

Publication Date	2002
Personal Author	Christian, D. C.
Page Count	12
Abstract	The most striking feature of BTeV, a dedicated b physics experiment which is expected to begin running in 2008 in the new CZero interaction region of the Fermilab Tevatron, is that the experiment will use data from a pixel vertex detector to recon- struct tracks and vertices for every beam crossing. The lowest level trigger will be an impact parameter trigger designed to identify events containing reconstructable decays of charm and bottom particles. An R&D program to develop a pixel readout chip optimized for the Tevatron was started at Fermilab in 1997, and is now nearing completion. The architecture of the BTeV pixel readout chip is described in this paper.
Keywords	Microelectronic circuits Raiation hardening Collider detectors Readout systems Architecture BTeV Pixel readout chips Dedicated b physics Fermilab Tevatron
Source Agency	Technical Information Center Oak Ridge Tennessee
Corporate Authors	Fermi National Accelerator Lab., Batavia, IL.; Department of Energy, Washington, DC.
Supplemental Notes	Sponsored by Department of Energy, Washington, DC.
Document Type	Technical Report
NTIS Issue Number	200318