Publication Date |
2014 |
Personal Author |
Herrmann, S.; Hart, P.; Dragone, A.; Freytag, D.; Herbst, R.; Pines, J.; Weaver, M.; Carini, G. A.; Thayer, J. B.; Shawn, O. |
Page Count |
4 |
Abstract |
After improving the PCB level electronics the next step in our continuing upgrade program of LCLS Cornell-SLAC Pixel Array Detector (CSPAD) cameras is the use of a new improved ASIC named CSPAD V1.5. The upgraded ASIC includes on chip DACs to set the bias currents of all amplifiers. The new chip also supports power cycling by design. Together this simplifies the PCB level complexity and eases the integration of many ASICs into one camera. Homogeneity across the full reticle size chip was improved by redesigning the power distribution. The upgrade included modifications of the gain latches and the per pixel comparators. Results from the upgraded cameras used at LCLS will be presented and discussed. |
Keywords |
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Source Agency |
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NTIS Subject Category |
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Corporate Authors |
Stanford Linear Accelerator Center, CA.; Department of Energy, Washington, DC. |
Supplemental Notes |
Sponsored by Department of Energy, Washington, DC. |
Document Type |
Technical Report |
NTIS Issue Number |
201425 |
Contract Number |
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